Author: Utilisateur

UNDERWATER FRONT END ELECTRONICS FOR PMm2

IPNO Participation: S. Drouet, B. Ky, J. Maltese, S. Tanguy, E. Wanlin
Collaboration : LAL/Omega Orsay, LAPP Annecy, Université Libre de Bruxelles

La couverture de très grandes surfaces de photodétection est un élément essentiel des dispositifs expérimentaux dévolus aux études des gerbes atmosphériques de grande énergie, des neutrinos de différentes sources (soleil, atmosphérique, supernova) et de la désintégration du nucléon. La génération suivante d’expériences ne pourra plus être le simple agrandissement de celles existantes utilisant des photomultiplicateurs (PM) connectés à un système centralisé de déclenchement et d’acquisition. Elle devra faire appel à des capteurs intelligents distribués; les partenaires de ce projet ANR se proposent de segmenter de très grandes surfaces en macro-cellules de 4*4 PM connectés à une électronique innovante autonome. Le service électronique de l’institut a conçu une carte sous marine hébergeant un Asic, réalisé par le pôle Omega/LAL ,et assurant la transmission des données vers une carte de surface développée au LAPP. Le SEP a également proposé un nouveau principe de TDC à 100ps pour la deuxième version de l’Asic.

Introduction
The next generation of neutrino experiments will be extensions by 10 or 20 times of the Super-Kamiokande detector. The photodetection will rely on hundreds of thousand of hemispherical photomultiplier tubes (PMTs) covering the surface of the tanks. As a consequence, the design must be driven by the costs and integrate industrial assembly procedures.It has been showed that important savings could be obtained by using 12 inch diameter PMTs instead of the 20 inch ones used in Super-Kamiokande. However, the increase in the number of electronics channel has to be compensated by using front-end integrated circuits and new data acquisition architecture.
For instance, the MEMPHYS project aims at constructing 3 or 4 Cerenkov water tanks, comprising about 80 000 PMTs each. The expected water height may be as important as 65 m, which creates a maximum pressure of 7.5 bar.Therefore, the requirement in the PMm2 project is set to 10 bars for safety.
The project name PMm2 summarizes the idea of paving the detector surface with square meter photodetection units.This R&D program is carried out by four laboratories (LAL/OMEGA, IPN, LAPP and ULB) and the Photonis company; it is funded by the french National Agency for Research (ANR) for 3.5 years, ending in June 2010.
Architecture
The 16 PMT are grouped in a unit, as shown in figure 1, and share a common submarine waterproof electronics, a common high voltage bias located close to the PMTs. A data cable for the connection with the surface electronics also carries the power voltage for the submarine electronics. The front end electronics consists in a ASIC, designed by LAL/Omega group for the first version, coupled to a FPGA that manages the dialog with the surface controller through the data cable.
Figure 1: 4*4 PMTs square meter photodetection unit
The detection relies on a Cerenkov cone that will produce a large circle much greater than a 16 PMTs cell; therefore it is impossible to provide a local trigger to the 16 channels electronics module, so charge and arrival time of all the pulses of each PMT is necessary. This triggerless mode implies a 100ns timestamp and a fine 1ns resolution TDC, in order to perform time coincidence and to obtain a good resolution for the reconstruction of the direction of the incident particle. This is achieved by transmitting a 10 MHz clock synchronized by GPS from the surface board through the 100 m data cable to the submarine board. A time calibration is then necessary.
Front end submarine electronics
The SEP took in charge the design of the submarine board in september 2008. The synoptic of the submarine board is showed in figure 2. The board hosts 2 main components: the Parisroc ASIC and an Altera Cyclone 3 FPGA. The submarine board is supplied in 48 V 30 W through the Ethernet link, Power Over Ethernet Plus. A DC/DC converter then realizes the translation 48 V / 5 V, and finaly different linear regulators create the 3.3 V, 2.5 V and 1.2 V necessary on board. A single high voltage converter produces the high voltage (up to 2 kV) to bias the PMTs, tunable from the surface. A 12 bits DAC ensures this functionnality.
Figure 2: synoptic of the submarine board
The ASIC achieves the compensation of the PMTs gain dispersion due to this common high voltage, the charge digitization on 12 bits, time stamping on 24 bits and fine time digitization on 12 bits also, for the 16 channels of PMTs. All the output data are read out in serial mode at a rate of 10 MHz.
The FPGA ensures the slow control of the ASIC from the surface, the data collection and the data transmission towards the surface, respecting a protocol made by LAPP (data are sent in Manchester code format). All the code is written in VHDL language. The 100 m data cable hosts 3 differential pairs: the first one is used for the unidirectionnal 10 MHz clock coming from the surface, the second one is bidirectionnal for the data (RS 485 format) and the third one is not used.
A temperature sensor allows a surface monitoring of the electronics temperature inside the waterproof enclosure.
A USB1 interface is embedded to allow the stand alone debugging of the board and the validation of the different functionnalities.
A local soft of acquisition has been designed and allows us to slow control the ASIC, to visualize energy spectra and collect time data.
The ASIC is hosted on a daughter board, including its own regulators and supply filters to avoid mother board digital noise pollution .
Special cares were taken in the design of the Printing Circuit Board (PCB) to meet rules of isolation due to the high voltage, rules of filtering, cooling and Electro Magnetic Compatibility (EMC). The board is a 8 layers one and obey to class 5 specifications.
The geometry of the enclosure of the electronics board was designed with the LAL to meet all the requirements due to pressure, EMC, cooling and waterproofing constraints. Under pressure tests up to 13 bars have been done to meet the final design. See figures 3.
A first complete set of test with 1 inch PMTs is actually under ambiant air tests to allow to calibrate the different charge gains on each channel; see in figure 4 the whole set of test. Next step will be under pressure water tests.
Because of problems concerning the analog part of the TDC (see the article PARISROC_V2 TDC improvement) and loss of events due to intrinsic architecture of the ASIC and 5 kHz noise pulses rate of PMTs, a second version of the ASIC has been designed. The second version of the daughter board hosting the ASIC has been realized and includes improvements in supplies filtering and distribution. The VHDL code is already modified to meet the new speed of 40 MHz serial output rate and new registers to slow control.
Figures 3: waterproof enclosure and submarine board
Figures 4: complete set of test with 1 inch PMTs